The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to vertical transistor structures.
Metal oxide semiconductor field-effect transistors (MOSFETs) include gate electrodes that are electrically insulated from operatively associated semiconductor channels by thin layers of dielectric material. MOSFETs having n-doped source and drain regions employ electrons as the primary current carriers while those having p-doped source and drain regions use holes as primary current carriers. Vertical transport field-effect transistors (VTFETs) have configurations wherein the current between the drain and source regions is substantially normal to the surface of the die. A vertical transport field-effect transistor may, for example, include a semiconductor pillar or fin having top and bottom regions comprising source/drain regions, the portion of the pillar between the source/drain regions defining a channel region. Junction field-effect transistors (JFETs) are characterized by doped, possibly vertical channel regions, p-n junctions on one or more sides of the channels, and ohmic contacts forming the source and drain regions.
Vertical transport FETs (VTFETs) are a promising alternative to standard lateral FET structures due to potential benefits, among others, in terms of reduced circuit footprint. A logic circuit comprising VTFETs can be referred to as a “vertical transport logic gate.” VTFETs can potentially provide electronic devices comprising logic circuits with improved circuit density. Such logic circuits can be characterized by a lower-number CPP (cell gate pitch) versus comparable logic circuits comprising lateral FET layouts. Minimum wiring pitch can also be relevant for realizing denser vertical FET layouts.
The growth of top spacers such as silicon nitride spacers during the fabrication of vertical transport field-effect transistors (VTFETs) can impair the reliability of such transistors. Shallow traps caused by damage to interfacial/high-k dielectric layers can cause such impairment of device reliability. Referring to FIG. 13A, an exemplary partially completed VTFET structure includes a semiconductor substrate 21, a semiconductor fin extending vertically with respect to the substrate 21, an epitaxial bottom source/drain layer 26A, and a bottom electrically insulating spacer 28 on the bottom source/drain layer. The bottom spacer is positioned between the bottom source/drain layer and a gate stack including gate dielectric and work function metal (gate electrode) layers 30, 32. An interfacial layer (IL) 31, for example silicon dioxide, forms part of the gate dielectric layer. A high-k dielectric material adjoins the interfacial layer 31. The deposition of a silicon nitride spacer 36 on the structure can result in fin (channel) oxidation, IL regrowth, and damage to the high-k gate dielectric layer, as schematically indicated by the column of x's in FIG. 13B. The method described below provides effective protection against oxygen diffusion and such resulting damage that may occur during top spacer deposition.